Integrated circuit

ABSTRACT

Integrated circuit which is integrated in a housing and has a plurality of connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit,  
     each connecting pin being connected via an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit,  
     where in order to minimize the line lengths of the associated wiring lines, the connecting pins ( 4 ) to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

CLAIM OF PRIORITY

[0001] Pursuant to 35 U.S.C. 119(a)-(d), this application claimspriority from German application no. 101 21 241.0, filed with the GermanPatent Office, Germany, on Apr. 30, 2001.

FIELD OF INVENTION

[0002] The invention relates to a circuit integrated in a housing, inwhich, in order to minimize the [lacuna] of the associated wiring lines,the connecting pins for high-frequency signals are fitted centrally tothe housing.

BACKGROUND

[0003] Following their production, integrated circuits are packaged in ahousing. Here, integrated circuits are considerably smaller than theassociated housing. The connecting pins for connecting the integratedcircuit to an external circuit, which pins are located on the housing,are connected via internal wiring lines to contact PADS in order to makeelectric contact with the electronic circuit.

[0004]FIG. 1 shows an arrangement according to the prior art. Theconnecting pins fitted to the housing are connected via wiring lines tocontact PADS on a circuit integrated in the housing. In this case, theconnecting pins are conventionally fitted in the manner of a matrix tothe underside of the housing. The contact PADS are located on a line ofsymmetry S, so that in the event of further miniaturization (shrink) ofthe integrated circuit within the housing, the position of the contactPADS can remain constant. The size of the integrated circuits or thechip size in the case of conventional chips is around 50 mm² The furtherthe miniaturization of integrated circuits progresses, the greater theline lengths become of the wiring lines to the external connecting pins.

[0005]FIGS. 2a, 2 b show the arrangement of connecting pins on theunderside of circuits integrated in housings, in accordance with theprior art.

[0006] In the arrangement according to the prior art, illustrated inFIG. 2a, the address lines ADR for addressing memory cells within theintegrated circuit, and the control signal connecting pins (CMD) forapplying control signals are arranged centrally, while the connectingpins are fitted above the data lines (Dq) in four groups in a peripheralposition on the underside of the housing.

[0007]FIG. 2b shows a further arrangement of connecting pins inintegrated circuits according to the prior art. In the arrangementillustrated in FIG. 2b, the address connecting pins ADR, the controlsignal connecting pins CMD and the data connecting pins DQ are likewisearranged in groups on the underside of the housing. In this case, thecontrol signal connecting pins are located in the center of the housing,while the address connecting pins and the data connecting pins arearranged peripherally. In this case, the data connecting pins DQ areconventionally fitted to the side on which there is a data connectingplug on the circuit board.

[0008] The disadvantage of the connecting pin arrangements illustratedin FIGS. 2a, 2 b is that the wiring lengths of the wiring lines betweenperipherally arranged connecting pins and the contact PADS within theintegrated circuit increase with increasing miniaturization of thecircuit integrated in the housing. Since, at the same time, theoperating clock frequencies of modern integrated circuits are increasingand, for example, are already some hundreds of MHz in modern DRAMmemories, so that data rates of more than 800 megabit per second canoccur, the line inductance of wiring lines between the connecting pinsand the contact PADS play an increasing role. The greater the lineinductance in the wiring lines, the lower the signal integrity of thesignal carried over the wiring line. As compared with the signalfrequencies of the data signals DQ, the signal frequencies of theaddress signals ADR and of the control signals CMD are comparativelylow.

[0009] The arrangements of the connecting pins illustrated in FIGS. 2a,2 b therefore exhibit the disadvantage that it is precisely the datasignals, which have a very high signal frequency, that are arranged in aperipheral position, so that because of the relatively great lengths ofthe wiring lines and the associated high line inductances, they have alow signal integrity and it is therefore possible for data transmissionerrors to occur.

SUMMARY

[0010] It is therefore the object of the present invention to provide anintegrated circuit which has high signal integrity, even at very highsignal frequencies.

[0011] The invention provides an integrated circuit which is integratedin a housing, comprising a plurality of connecting pins fitted to thehousing for connecting the housing to signal lines of an externalcircuit,

[0012] each connecting pin being connected via an associated wiring lineto a contact PAD of the circuit integrated in the housing, to exchangesignals between the external circuit and the integrated circuit,

[0013] the integrated circuit according to the invention beingcharacterized in that in order to minimize the line lengths of theassociated wiring lines, the connecting pins to be connected to signallines for high-frequency signals are fitted centrally to the housing.

[0014] In a further preferred embodiment of the integrated circuitaccording to the invention, the connecting pins are fitted in a mannerof a matrix to the circuit integrated in the housing.

[0015] The line inductance of the wiring lines for connecting theintegrated circuit to the signal lines for high-frequency externalsignals is preferably minimal.

[0016] In a particularly preferred embodiment of the integrated circuitaccording to the invention, the contact PADS are arranged along a lineof symmetry on the housing.

[0017] In a further particularly preferred embodiment of the integratedcircuit according to the invention, the data connecting pins to beconnected to data signal lines and the associated ground connecting pinsare arranged along the line of symmetry in a central position on thehousing.

[0018] In a further preferred embodiment of the integrated circuit, theclock connecting pins to be connected to clock signal lines and theassociated ground connecting pins are arranged in groups along a line ofsymmetry in a central position on the housing.

[0019] In a further preferred embodiment of the integrated circuitaccording to the invention, address connecting pins to be connected toaddress signal lines and the associated ground connecting pins arearranged in groups in a peripheral position on the housing.

[0020] In a further preferred embodiment of the integrated circuitaccording to the invention, the control connecting pins to be connectedto control signal lines and the associated ground connecting pins arefitted in groups in a peripheral position on the housing.

[0021] In a further preferred embodiment of the integrated circuitaccording to the invention, the data connecting pins and the clockconnecting pins to be connected to clock signal lines are arranged closeto one another.

[0022] In a particularly preferred embodiment of the integrated circuitaccording to the invention, the line inductances of wiring lines for theconnecting pins to be connected to external signal lines forhigh-frequency signals are some nhenry smaller than the line inductancesof wiring lines of the connecting pins to be connected to externalsignal lines for low-frequency signals.

[0023] In a particularly preferred embodiment of the integrated circuitaccording to the invention, the line inductances of wiring lines of theconnecting pins to be connected to signal lines for high-frequencysignals are less than 3.25 nhenry.

[0024] In a particularly preferred embodiment of the integrated circuitaccording to the invention, the integrated circuit is an integratedmemory, which is packaged in a housing which has address connecting pinsfor addressing memory cells, data connecting pins for data transmission,control signal connecting pins for control signal transmission, groundconnecting pins and clock signal connecting pins.

[0025] Preferred embodiments of the integrated circuit according to theinvention will be described below with reference to the appended figuresin order to explain features essential to the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 shows a wiring arrangement according to the prior art;

[0027]FIG. 2 shows an arrangement of connecting pins in a housing of aconventional integrated circuit;

[0028]FIGS. 3a, 3 b show embodiments of the integrated circuit accordingto the invention.

DETAILED DESCRIPTION

[0029]FIG. 3a shows a first embodiment of the integrated circuitaccording to the invention. In the embodiment illustrated in FIG. 3a,the integrated circuit 1 is an integrated memory module. The integratedmemory module 1 has address connecting pins 2 a, 2 b, 2 c, 2 d andassociated ground connecting pins, which are arranged in a peripheralposition at corners of the housing. The address connecting pins 2 [sic],2 b, 2 c, 2 d are connected via wiring lines to associated contact PADS,contained in the housing, to make contact with the integrated circuit 1contained in the housing. The memory module 1 also has control signalconnecting pins 3 a, 3 b to be connected to control signal lines. Inaddition, data connecting pins 4 are provided along a line of symmetry Sof the housing 1, via which pins the memory module exchanges data withthe external circuit. The data connecting pins to be connected to thedata signal lines of the external circuit and the associated groundconnecting pins are arranged along the line of symmetry S in a centralposition on the housing of the integrated circuit 1. In this way, thelengths of the associated wiring lines via which the high-frequency datasignals are exchanged between the integrated circuit 1 and an externalcircuit are minimal. Consequently, the line inductances of the wiringlines for the data signals are likewise minimal, so that signalintegrity is ensured even for the very high-frequency data signals whichoccur at data transmission rates of, for example, 800 Megabit persecond.

[0030] The connecting pin configuration illustrated in FIG. 3a is alsodesignated an OAIC configuration (OAIC: Outer Address Inner Command).The line inductances of the wiring lines for connecting the integratedcircuit 1 to signal lines for the high-frequency data signals areminimal, while the line inductances of the wiring lines to the addresssignal lines for the relatively low-frequency address signals arecomparatively high. On account of the relatively low signal frequency ofthe address signals applied, however, the relatively high lineinductances do not have a disruptive effect on the operation of theintegrated memory module 1. The line inductances of the wiring lines forconnecting pins to be connected to the data signal lines for dataexchange are lower than 3.25 nhenry in a particularly preferredembodiment of the integrated circuit according to the invention, so thatdata transmission rates of more than 800 Megabit per second arepossible. Because of the symmetrical arrangement of the connecting pinson the housing, the line inductances of the connecting pins placed atthe center for the high-frequency signals are constant in the event oftechnology-induced shrinking of the integrated circuit contained in thehousing, while the line inductance of the connecting pins of thelow-frequency signals increases.

[0031] The connecting pins for the various signals are fitted in themanner of a matrix to the underside of the housing of the integratedcircuit 1. In this case, the connecting pins for the various functions,that is to say for example the address connecting pins, the controlconnecting pins, the data connecting pins and the associated ground andclock signal connecting pins, are arranged in groups on the housing.

[0032]FIG. 3b shows an alternative embodiment of the integrated circuit1 according to the invention. In the embodiment shown in FIG. 3b, thecontrol connecting pins and the address connecting pins are arranged ingroups 5 a, 5 b, 5 c, 5 d in a peripheral position at the corners of thehousing. The wiring lines for the relatively low-frequency addresssignals and control signals are therefore relatively high. Furthermore,the data connecting pins the [sic] in the embodiment shown in FIG. 3bare arranged in four groups 6 a to d in a central position symmetricallywith respect to the line of symmetry S. Furthermore, clock signalconnecting pins are fitted in a group 7 symmetrically with respect tothe line of symmetry S on the underside of the housing.

[0033] By means of the connecting pin arrangement shown in FIG. 3b, thedata connecting pins are arranged in relation to the associated clocksignal connecting pins in such a way that the propagation timedifferences between a data signal and an associated clock signal areminimal.

Having described the invention, and a preferred embodiment thereof, whatis claim as new, and secured by letters patent is:
 1. Integrated circuitwhich is integrated in a housing and has a plurality of connecting pinsfitted to the housing for connecting the housing to signal lines of anexternal circuit, each connecting pin being connected via an associatedwiring line to a contact pad of the circuit integrated in the housing,to exchange signals between the external circuit and the integratedcircuit, characterized in that in order to minimize the line lengths ofthe associated wiring lines, the connecting pins (4, 6, 7) to beconnected to signal lines for high-frequency signals are fittedcentrally to the housing.
 2. Integrated circuit according to claim 1,characterized in that the connecting pins (2, 3, 4, 5, 6, 7) are fittedin the manner of a matrix to the housing of the integrated circuit (1).3. Integrated circuit according to claim 1 or 2, characterized in thatthe line inductances of the wiring lines for connecting the integratedcircuit (1) to signal lines for high-frequency signals are minimal. 4.Integrated circuit according to one of the preceding claims,characterized in that the contact PADS are arranged along a line ofsymmetry (S) of the housing.
 5. Integrated circuit according to one ofthe preceding claims, characterized in that the data connecting pins (4)to be connected to data signal lines and the associated groundconnecting pins are arranged in groups along the line of symmetry (S) ina central position on the housing.
 6. Integrated circuit according toone of the preceding claims, characterized in that the clock signalconnecting pins (7) to be connected to clock signal lines and theassociated ground connecting pins are arranged in groups along the lineof symmetry (5) in a central position on the housing.
 7. Integratedcircuit according to one of the preceding claims, characterized in thatthe address connecting pins (2) to be connected to address signal linesand the associated ground connecting pins are fitted in groups in aperipheral position on the housing.
 8. Integrated circuit according toone of the preceding claims, characterized in that the control signalconnecting pins (5) to be connected to control signal lines and theassociated ground connecting pins are arranged in groups in a peripheralposition on the housing.
 9. Integrated circuit according to one of thepreceding claims, characterized in that the data connecting pins (4, 6)and the clock signal connecting pins (7) are arranged close to oneanother on the housing.
 10. Integrated circuit according to one of thepreceding claims, characterized in that the line inductances of thewiring lines of the connecting pins (4, 6, 7) to be connected to signallines for high-frequency signals are lower by some nanohenry than theline inductance of the wiring lines of the connecting pins (2, 3, 5) tobe connected to signal lines for low-frequency signals.
 11. Integratedcircuit according to one of the preceding claims, characterized in thatthe line inductance of the wiring lines of the connecting pins (4, 6, 7)to be connected to signal lines for high-frequency signals are less than3.25 nhenry.
 12. Integrated circuit according to one of the precedingclaims, characterized in that the integrated circuit (1) is a memory.13. Housing for an integrated circuit, in which, in order to minimizethe line lengths of associated internal wiring lines, connecting pinsfor connecting the housing to external signal lines for high-frequencysignals are fitted centrally to the housing.